1. Field of the Invention
The present invention relates to a delay-locked loop (DLL) and a method of using the DLL. More particularly, the present invention relates to using a DLL in low-frequency applications.
2. Description of the Related Art
In general, a clock signal is used as a reference for adjusting the operational timing in a system or circuit, and also used to perform a faster operation without errors. When an external clock is used inside the system or circuit, a time delay (clock skew) occurs because the external clock signal has to pass many circuits and components to reach the inside circuits. A DLL compensates for the time delay, so that the internal clock signal can have the same phase as that of the external clock signal.
FIG. 1 is a schematic diagram showing a conventional DLL 100. The DLL 100 receives an external clock signal XCLK, outputs an internal clock signal ICLK, and includes a variable delay line 110, a phase detector 120, and a control circuit 130. The variable delay line 110 delays the external clock signal XCLK for a specific delay time and outputs the delayed external clock signal as the internal clock signal ICLK. The phase detector 120 compares the phase of the external clock signal XCLK and the phase of the internal clock signal ICLK and outputs the result of the comparison. The control circuit 130 adjusts the specific delay time of the variable delay line 110 according to the result of the comparison in order to synchronize the internal clock signal ICLK with the external clock signal XCLK.
The operational range of the DLL 100 is determined by the range of delay time of the variable delay line 110. In general, the operational range of a DLL is prescribed by the specification of the system or circuit to which the DLL belongs. For example, if the DLL 100 is a part of a double data rate synchronous dynamic random access memory (DDR SDRAM) and the maximum period of the clock of the DDR SDRAM is 15 nanoseconds, the DLL 100 cannot be normally operated according to a clock period over 30 nanoseconds.
For example, FIG. 2 is a schematic diagram showing a possible scenario of the clock signals XCLK and ICLK in the conventional DLL 100, wherein Tck is the period of the external clock signal XCLK and Tloop_max is the maximum loop delay of the DLL 100. In other words, Tloop_max is the maximum trip time spent by the external clock signal XCLK for one complete loop in the DLL 100. As shown in FIG. 2, the goal of the DLL 100 is aligning the positive edge TP of the internal clock signal ICLK to the positive edge TK of the external clock signal XCLK. However, aligning TP to TK is impossible because Tck is much longer than Tloop_max is.
When testing a DDR SDRAM, the clock frequency of the test apparatus is too low compared to the clock frequency of normal operation for the DLL to work properly. It is thus impossible to perform logic verification relating to the DLL or defect analysis on the DDR SDRAM in the wafer level. Since the test in the wafer level is incomplete without verification relating to the DLL, this results in a low yield in the package level.